6809 CPU



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6809 MICROPROCESSOR

6809 1Mz clock, 68A09 1.5MHz clock, 68B09 2.0MHz (68x09E variants NOT pin compatible)

2x 16-bit Index registers - X an Y

2x Indexable stack pointers - User stack and standard hardware stacks

2x 8-bit Accumulators can be concatenated to form 1x 16 bit Accumulator

The 8-bit direct page register can be set to work from anywhere in memory


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Memory Map for interrupt vectors:

FFFE	FFFF	Reset
FFFC	FFFD	Non maskable interrupt
FFFA	FFFB	Software interrupt 1
FFF8	FFF9	Interrupt request
FFF6	FFF7	Fast Interrupt request
FFF4	FFF5	Software interrupt 12
FFF2	FFF3	Software interrupt 13

Pin descriptions:

1	Vss	Ground
2	/NMI	Non-maskable interrupt	Negative edge triggered
3	/IRQ	Interrupt request	If I condition bit is not masked Low level trigger
4	/FIRQ	Fast Interrupt request	F condition bit will mask. Faster response than IRQ
5	BS	Bus Status signal (out)	When decoded with BA shows current MPU state
6	BA	Bus Available (out)	MPU state signal (As above)
7	Vcc	+5V

8-20	A0-12	Address lines
21-23	A13-15	Address lines	All lines go tristate when Bus Available is high
24-31	D0-7	Data bus	Bi-directional
32	R / W	Read write line	Indicates direction of current data transfer
33	/DMA	Memory control	DMA operation or memory refresh
34	E	Clock input	Combined with Q provides 6809's timing
35	Q	Clock input	As above
36	MRDY	Memory control	Extends memory access time for slow memory
37	/RES	Reset	Active low resets 6809 to FFFE and FFFFh
38	EXTAL	Osc1	Crystal (1) or external oscillator
39	XTAL	Osc2	Crystal (2)
40	/HALT	Halt	Low level causes MPU to stop running



		Peripheral circuitry


	Z280 and Central Heating Controllers

When using the 6809 in a straightforward application, begin by connecting the pins as follows:

TIE HIGH: 2, 3, 4, 7, 33, 36, 40 TIE LOW : 1 NO CONNECT: 5, 6

USE: Vcc, Vss, E (and maybe Q), R /W, /RES, Address and Data Busses, plus the 2x crystal connections or external TTL level oscillator into pin 38

* Remember that the hardware reset takes the program counter initially to FFFE and FFFF so allow for this when defining the ROM address. If an 8K ROM device is to be used here, then a good starting point would be to connect a 74LS138 decoder up to address lines A13/14/15, which may be used to enable the ROM, the RAM (up to 8K with this configuration) and another 6 addresses (perhaps for I/O) without any further hardware.



Concluding ideas


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