1

Pick up the list of instructions.

In programming, this is the hardware RESET. The micro turns to page ONE (the starting address) in the READ ONLY MEMORY (ROM)

2

Instruction one says go to the letter box with the 6 on it, make a perfect COPY of what�s inside and put it in your pocket.

In a program this would be an I/O (input / output) command. Go and READ in a value from a specific  ADDRESS and place it in a REGISTER

3

Instruction two says put a COPY of what is in your pocket into the letter box with the 9 on it

Another I/O instruction. But this time it tells the micro to COPY what it happens to have in it�s register into a different ADDRESS

4

Instruction three says stand still and stop reading the instructions!

This is the equivalent of a HALT instruction. Not one of the more commonly used ones, but there to be obeyed all the same.

Let�s quickly compare the two port ideas then. The more complex with it�s decoder chip, is using two ADDRESS lines from the micro to decode the correct address. The R/W line is then applied to the CLOCK line of the decoder. A NEGATIVE EDGE signal will probably be needed here. Note that the processor READ / WRITE line only enables the decoder during a processor WRITE - hence this is a simple OUTPORT circuit.

In the second simpler example, as this is a barebones method with few hardware RESOURCES, we can use the unused address line A15 without the decoder. Note though that the hardware will require a NEGATIVE signal as before, so as the ADDRESS lines are generally POSITIVE going, we need to wire in an INVERTER gate before applying the address signal to the buffer�s  Chip Enable. If an OCTAL BUFFER chip is used here, we have a simple INPORT circuit.

A quick word about TRISTATE for those who may be unsure of it�s meaning. Without the ability to TRISTATE bus devices, microprocessor�s as we know them could not exist. If you remember that the processor�s DATA BUS lines will be connected to (at the very least), three or more devices at once, by making these devices tristate, we allow any OUTPUTS on the bus to go high-impedance - i.e. their customary output voltages are not permitted to interfere with the activity on the bus that does not concern them. Using the tristate enable lines, we are able to physically SELECT the HARDWARE of our choice onto the bus only when it is called for.

INTERFACING I/O DEVICES

I/O devices are accessed in much the same way as the memory, though they sometimes need addressing by an external addressing device or decoder. The most basic devices being simply latches or even buffers, enabled by a decoder or I/O line. In the case of the TIL311 display device  shown above, the package incorporates not only the LED segments, but also the binary to segment decoder AND a data latch! You can see the actual chip itself in the bottom half of the device. All in all, a very easy and convenient display to use, as all one does is connect it�s four data lines straight up to the processors data bus, and the strobe to the I/O decoder. Voila! Note that it only has four data lines, so you have to decide whether to connect to the top half of the bus or the lower half. Of course if using two TIL311�s, one could use the LOWER four bits for one display and the UPPER four bits for the other. By commoning the enable lines, one could then update them in the program simultaneously from the same byte! (assuming an 8 bit processor)

Although PIO and PIA multi I/O LSI chips offer many different interfacing options, as a general rule, I tend to avoid them unless these facilities (such as interrupts) are really needed, as it is usually simpler to use either two or three tri-state latches or buffers. The ones I most commonly use are the 74xx373 or 374 octal latches, or the 74xx240 241 244 series octal buffers. Where bi-directional tri-state buffers are needed - such as that required with a multiplexed data / address bus, I generally opt for the 74xx245. Where space is at a premium and if only 4 bits are needed, the 74xx125 is a viable alternative tri-state device in a 14 pin pack. (The others all mentioned above are 20 pin.)

INTERFACING MEMORY DEVICES

Memory is something that all micro�s need to interface to. It will be noticed that there is almost a �standard� for the pin layout used by most of these - which can be very useful at times. Have a look at a few of the pinouts in the Data Sheets section to see for yourself.

Memory is connected by it�s ADDRESS and DATA lines to the processor and accessed via it�s chip select and memory read / write lines. This is where the chips vary a little with capacities and type. Almost ALL will be accessed by taking their enable lines LOW. Read / Write lines invariably need the line taken low to WRITE.

A memory device may have more select lines than you need - i.e. /CE1 (chip enable 1) /CE2 (chip enable 2) and /OE (output enable) etc. You only have to use those that you need. Simply hard-wire-enable the ones that you don�t need, remembering that an output enable (for example) can�t enable anything if the chip itself is not enabled with the /CE lines.

Of course there is nothing exactly difficult in inserting buffering devices in the bus, (as long as one remembers to add in their propogation delay when calculating timing values), it�s really just the extra drag of wiring the things in! The best way to ensure that your circuits won�t need them is to use HC (high speed CMOS) devices wherever possible.